The present invention relates to an MOS transistor with an increased breakdown voltage (which will be herein called a xe2x80x9chigh-voltage MOS transistorxe2x80x9d) and a method for fabricating the transistor.
Various structures have been specially designed for a high-voltage MOS transistor. Among other things, a LOCOS off-set structure is particularly effectively applicable to an MOS transistor, of which the gate, source and drain all have to have an increased breakdown voltage (e.g., as in a liquid crystal display driver). In the LOCOS offset structure, a relatively thick field oxide film (typically, a locally oxidized silicon (LOCOS) film) is formed around the edges of the gate electrode of an MOS transistor or between the gate electrode and source/drain regions thereof.
The LOCOS offset structure includes offset regions and well offset regions. The offset regions together form a lightly-doped layer under the LOCOS regions that are located around the edges of a gate electrode. These offset regions are provided mainly to prevent the intensity of an electric field from increasing too much at the pn junction between the drain region and a region under the gate electrode. The off-set regions are of the same conductivity type as the source/drain regions but doped more lightly than the source/drain regions. The well offset regions also form a lightly-doped layer under the source/drain regions, but are located deeper than the offset regions. These well offset regions are provided mainly to prevent the intensity of an electric field from increasing too much in the pn junction between the drain region and a well or a substrate region of the opposite conductivity type under the drain region. The well offset regions are also of the same conductivity type as the source/drain regions and the offset regions but are doped even more lightly than the offset regions. That is to say, the source/drain, offset and well offset regions are all of a conductivity type, but their dopant concentrations decrease in this order. Specifically, the source/drain regions have the highest dopant concentration, the offset regions have the next highest and the well offset regions the lowest.
Hereinafter, a known high-voltage MOS transistor with the LOCOS offset structure will be described with reference to FIGS. 11 and 12. FIGS. 11 and 12 are respectively a cross-sectional view and a plan view illustrating the known high-voltage MOS transistor. As shown in FIGS. 11 and 12, the high-voltage transistor is normally formed along with a transistor with a low breakdown voltage (which will be herein called a xe2x80x9clow-voltage transistorxe2x80x9d) on the same chip. In the example illustrated in FIGS. 11 and 12, the high- and low-voltage transistors a and b are implemented as an n-channel MOS transistor (NMOS) and a p-channel MOS transistor (PMOS), respectively.
First, the structure of the high-voltage transistor a will be described. A p-well 2 is defined for the high-voltage NMOS a inside a p-type substrate 1 and a gate electrode 8 is formed over the p-well 2 with a gate oxide film 7 interposed therebetween. LOCOS regions 6 are formed around the edges of the gate electrode 8 and between the gate electrode 8 and source/drain regions 9s and 9d to electrically isolate the gate electrode 8 from the source/drain regions 9s and 9d on the surface of the substrate 1. Source/drain offset regions 4s and 4d are provided under the LOCOS regions 6 around the edges of the gate electrode 8. And source/drain well offset regions 3s and 3d are further provided under the source/drain regions 9s and 9d. The source offset and well offset regions 4s and 3s are not always needed because, normally, the intensity of an electric field should not increase so much on the source side according to ordinary specifications. However, a transistor device is usually formed symmetrically to have source/drain regions of the same length and with the same dopant concentration. This is because the source/drain regions should not be fixed but are preferably used interchangeably. That is to say, the lengths Ls and Ld of the source/drain offset regions 4s and 4d are preferably equal to each other. In addition, the length 0d of a region overlapping between the drain offset and well offset regions 4d and 3d is also equal to the length 0s of a region overlapping between the source offset and well offset regions 4s and 3s. In this structure, the gate, source and drain regions of the NMOS a are electrically isolated from a channel stopper 10, which is a doped layer for creating a potential in the p-well 2, by n- and p-type isolating regions 4 and 5 and LOCOS regions 6.
Next, the structure of the low-voltage transistor b will be described. An n-well 3 is defined for the low-voltage PMOS b inside the p-well 2. Another gate electrode 8 is formed over the n-well 3 with the gate oxide film 7 interposed therebetween, and source/drain regions 11s and 11d are defined on the left- and right-hand sides of the gate electrode 8. In this structure, the gate, source and drain regions of the PMOS b are electrically isolated from a channel stopper 12, which is a doped layer for creating a potential in the n-well 3, by the n- and p-type isolating regions 4 and 5 and the LOCOS regions 6.
Hereinafter, a method for fabricating the known high-voltage MOS transistor with the LOCOS offset structure will be described with reference to FIGS. 13(a) through 13(d).
First, as shown in FIG. 13(a), the p-well 2 is defined in the surface region of the p-type substrate 1 by photolithography, ion implantation and annealing processes. Next, as shown in FIG. 13(b), the n-well 3 and the source/drain well offset regions 3s and 3d are defined in respective surface regions of the p-well 2 by photolithography, ion implantation and annealing processes. Subsequently, as shown in FIG. 13(c), the n- and p-type isolating regions 4 and 5 and the source/drain offset regions 4s and 4d are formed in the upper parts of the p-well 2 by photolithography and ion implantation processes. Then, the LOCOS regions 6 are formed to cover these regions. Thereafter, as shown in FIG. 13(d), the gate oxide film 7 and the gate electrodes 8 are formed on the surface of the substrate 1. Finally, the source/drain regions 9s and 9d and 11s and 11d and the channel stoppers 10 and 12 are formed by photolithography, ion implantation and annealing processes. In this manner, the high- and low-voltage MOS transistors a and b are formed on the same chip.
Next, it will be described how the known high-voltage MOS transistor with the LOCOS offset structure operates. When a high voltage is applied to the gate electrode 8 and the drain region 9d, the high-voltage NMOS a turns ON. Then, not only the drain region 9d but also the drain offset and well offset regions 4d and 3d, which are lightly-doped layers of the same conductivity type as the drain region 9d, are depleted. Thus, it is possible to prevent the intensity of an electric field from increasing too much locally around the drain region 9d. As a result, the breakdown voltage of the NMOS a can be increased sufficiently.
In the known structure, however, a substrate potential VW easily exceeds a source potential VS. More exactly, the substrate potential VW minus the forward biased breakdown voltage of silicon often exceeds the source potential VS. Accordingly, a breakdown voltage, causing avalanche breakdown of a transistor called xe2x80x9csustaining breakdownsxe2x80x9d (which will be herein called a xe2x80x9csustaining breakdown voltagexe2x80x9d), is adversely low.
Hereinafter, it will be described with reference to FIGS. 14(a) and 14(b) how and when the sustaining breakdown occurs in the known high-voltage MOS transistor with the LOCOS offset structure. In the following description, the sustaining breakdown of the NMOS a will be explained for illustrative purposes. FIGS. 14(a) and 14(b) illustrate how the known high-voltage MOS transistor operates. Specifically, FIG. 14(a) is a cross-sectional view of the transistor in operation, while FIG. 14(b) is a graph showing a relationship between the drain voltage and the current.
As shown in FIG. 14(a), although voltages are applied to the high-voltage MOS transistor at the electrode terminals G, D2, S2 and W2, it is regions G, D1, S1 and W1 under the gate electrode 8 that actually operate as the gate, drain, source and well of the transistor. Accordingly, the mechanism of the sustaining breakdown will be described with our attention mainly focused on these regions. The electrode terminals D2, S2 and W2 are separated from the regions D1, S1 and W1, actually serving as the drain, source and well of the transistor, with resistance components RD, RS and RW for the drain and source offset regions 4d and 4s and the p-well 2 interposed therebetween. These resistance components RD, RS and RW are provided to prevent the intensity of an electric field from increasing too much.
When a positive voltage is applied to the gate electrode 8 and the drain region 9d, the high-voltage MOS transistor turns ON. As a result, not only the drain region 9d but also the drain offset and well offset regions 4d and 3d, which are lightly-doped layers of the same conductivity type, are depleted. When these regions 3d, 4d and 9d are sufficiently depleted by further increasing the voltage applied, electrons, which are the majority carriers in the n-type regions, start to move from the source toward the drain and a drain current ID1 starts to flow. Part of the drain current ID1 flows toward the source region 9s, which current will be herein called a xe2x80x9csource current IS1xe2x80x9d. And the other part of the drain current ID1 flows vertically toward the well 2 and the substrate 1 which current will be herein called a xe2x80x9csubstrate current IW1xe2x80x9d. That is to say, ID1=IS1+IW1. It should be noted that the substrate current is usually labeled as Isub, but is herein identified by IW1. The relationship between the drain voltage VD1 and the current ID1 is shown in FIG. 14(b). As can be seen from FIG. 14(b), while the drain voltage VD1 is relatively low, the drain current ID1 is approximately equal to the source current IS1 and almost no substrate current IW1 flows.
However, as the drain voltage VD1 increases, electrons, moving around the drain, are accelerated by the electric field with an intensity increased by the drain voltage VD1 and collide against the lattice sites of silicon to create electron-hole pairs. The holes created in this manner are swept by the electric field toward the well and the substrate. As a result, the substrate current IW1 starts to flow. This substrate current IW1 and the resistance component RW of the p-well 2 change the substrate voltage VW1. That is to say, since the substrate current IW1 is flowing, the substrate potential VW1 (=RWxc2x7IW1) is created in the well and is much higher than the source potential VS1, because the source potential VS2 is fixed at 0 V. As a result of this variation in substrate voltage VW1, the substrate voltage VW1 minus the forward biased breakdown voltage of silicon comes to exceed the source voltage VS1 and the pn junction between the substrate and the source is forward biased. That is to say, in this case, the regions S1, W1 and D1 serve as emitter, base and collector for a parasitic bipolar transistor, not as the source, well and drain for the MOS transistor. And since the parasitic bipolar transistor turns ON, the amount of current flowing starts to rise abruptly. Thereafter, as the drain voltage VD1 increases, the substrate current IW1 goes on increasing steeply. And when the drain voltage VD1 reaches x volts, the drain current ID1 reaches a current value causing breakdown of the transistor. As a result, sustaining breakdown occurs. This value x of the drain voltage VD1 is the sustaining breakdown voltage of the known high-voltage MOS transistor.
It is therefore an object of the present invention to provide a high-voltage MOS transistor that can have its sustaining breakdown voltage increased while maintaining good characteristics and a method for fabricating the transistor.
To achieve this object, according to the inventive high-voltage MOS transistor and its fabrication process, the source resistance value RS1 is appropriately controlled, thereby preventing the substrate voltage VW1 minus the forward biased breakdown voltage of silicon from exceeding the source voltage VS1. As a result, an MOS transistor with an increased sustaining breakdown voltage and its fabrication process can be obtained.
To avoid the sustaining breakdown, the substrate voltage VW1 minus the forward biased breakdown voltage of silicon should be kept equal to or less than the source voltage VS1 by intentionally changing at least one of the parameters included in the equations of VW1=RW1xc2x7IW1 and VS1=RSxc2x7IS1. However, the source current IS1 and the substrate current IW1 are determined substantially univalently by the drain voltage VD1 and are not changeable arbitrarily. Also, the resistance RW of the p-well 2 is determined according to the constraints that should be met to realize the characteristics expected of the MOS transistor and is not changeable either for just the purpose of increasing the sustaining breakdown voltage. The same statement is not applicable to the source resistance RS though. As described above, the source resistance RS is normally set equal to the drain resistance RD because the source/drain regions are usually designed to have the same length and the same dopant concentration. This symmetrical arrangement is adopted just to simply the design process. Accordingly, generally speaking, the source/drain regions do not always have to have the same length and the same concentration to realize good characteristics for the transistor. The drain offset region, implementing the drain resistance RD, is provided to prevent the intensity of an electric field from increasing too much when depleted upon the application of the drain voltage VD1. The value of the drain resistance RD is limited by the drain voltage, the operating speed of the transistor and the ON resistance characteristics. In contrast, the value of the source resistance RS is not limited so much and changeable relatively easily, because the source resistance RS is defined with the source potential VS2 fixed at zero volts, not with a high electric field applied unlike the case of the drain resistance RD.
For these reasons, it can be seen that only the source resistance value RS is regulable arbitrarily. By appropriately setting the source resistance value RS independently of the drain resistance value RD, the source voltage VS1 can be increased, and therefore, the substrate voltage VW1 minus the forward biased breakdown voltage of silicon can be kept equal to or less than the source voltage VS1. As a result, it is possible to avoid the sustaining breakdown.
In the known high-voltage MOS transistor, the drain resistance value RD is set to an appropriate value to realize ideal transistor characteristics. However, since the source/drain regions have been formed symmetrically just to simply the fabrication process or the circuit specifications, the source resistance value RS has not been set to its best value. Thus, according to the present invention, the source resistance value RS is adaptively changed into a most desirable value, thereby providing a high-voltage MOS transistor and its fabrication process that can easily increase the sustaining breakdown voltage while ensuring good characteristics for the MOS transistor.
In the MOS transistor of the present invention, the source/drain regions might have an asymmetrical structure or asymmetrical dopant concentration profile, but there will be no problems even in that situation. In general, in a low-voltage MOS transistor to be driven at 5 V, for example, the source/drain regions are formed symmetrically in the gate longitudinal direction. This is simply because such a symmetrical structure, in which the source/drain regions are usable interchangeably, is advantageous to increase the flexibility of circuit specifications. In contrast, as for a high-voltage transistor, the design process of the circuit will not be affected even if the source/drain regions are defined non-interchangeably. Accordingly, the source/drain regions may have mutually different resistance values or an asymmetrical structure in the gate longitudinal direction.
To increase the sustaining breakdown voltage, an external resistor has often been formed for the source region in the prior art. However, according to the present invention, there is no need to provide such an external resistor. And yet the same effects as those of the known transistor with the external resistor are still attainable by taking advantage of the resistance of an offset region for an MOS transistor with the LOCOS offset structure in its source/drain regions.
Specifically, an inventive high-voltage MOS transistor is characterized in that a resistance value of a source region is set independently of a resistance value of a drain region in such a manner as to increase a sustaining breakdown voltage of the transistor.
In one embodiment of the present invention, a resistance value of a source offset region is set independently of a resistance value of a drain offset region in such a manner as to increase the sustaining breakdown voltage of the transistor.
Another inventive high-voltage MOS transistor includes a drain offset region and a source offset region, which is asymmetrical to the drain offset region, such that the transistor has a high sustaining breakdown voltage.
In one embodiment of the present invention, a size of the source offset region is not equal to a size of the drain offset region such that the transistor has the high sustaining breakdown voltage.
In another embodiment of the present invention, a dopant concentration of the source offset region is not equal to a dopant concentration of the drain offset region such that the transistor has the high sustaining breakdown voltage.
Still another inventive high-voltage MOS transistor includes a drain offset region and a source offset region, which has a dopant concentration different from that of the drain offset region, such that the transistor has a high sustaining breakdown voltage.
In one embodiment of the present invention, the resistance value of the source region is set higher than that of the drain region such that a substrate voltage VW minus a forward biased breakdown voltage of silicon does not exceed a source voltage VS easily.
An inventive method for fabricating a high-voltage MOS transistor includes the steps of: defining a resist pattern that makes a size of a source offset region greater than a size of a drain offset region; and forming the source and drain offset regions using the resist pattern to increase a sustaining breakdown voltage of the transistor.
Another inventive method for fabricating a high-voltage MOS transistor includes the steps of: forming a drain offset region; and forming a source offset region by implanting dopant ions at such a level as setting a dopant concentration of the source offset region independently of a dopant concentration of the drain offset region to increase a sustaining breakdown voltage of the transistor.
In one embodiment of the present invention, the dopant concentration of the source offset region is set lower than that of the drain offset region.
Still another inventive method for fabricating a high-voltage MOS transistor, which will be formed along with a low-voltage MOS transistor on the same chip, includes the steps of: shifting a photomask for forming a well for the low-voltage MOS transistor and source and drain well offset regions for the high-voltage MOS transistor to such a position as making a size of a region overlapping between the source well offset region and a source offset region smaller than that of a region overlapping between the drain well offset region and a drain offset region; and forming the source and drain well offset regions for the high-voltage MOS transistor using the photomask to increase a sustaining breakdown voltage of the high-voltage MOS transistor.
In the inventive high-voltage MOS transistor and its fabrication process, a resistance value of the source region is set independently of that of the drain region. Accordingly, a voltage value obtained by subtracting the forward biased breakdown voltage of silicon from the substrate voltage VW is much less likely to exceed the source voltage VS. As a result, it is possible to increase the sustaining break-down voltage of the MOS transistor while ensuring good characteristics for the transistor.